14. Electronics
Electronics for the LHC project falls into the following categories:
Interlocks, critical timing, PIC-based µCs, optical drivers, optical detectors, reference sources, experimental circuits.
Initially I planned to generate critical timing delays using dedicated Microchip PIC µCs under control of the system GUI (Graphical User Interface) as this requires minimal hardware and asserts all control from a central point.
Later I realised I would need some delays to be controllable in the order of nanoseconds and instead considered loading a Cypress CY7C4261V 16kx9-bit FIFO memory from the PIC and clocking the data out at 100MHz (10ns clock), again relatively easy to build and still software controllable.
This mutated further when I became concerned by potential EMI from high energy transitions on laser flashlamp triggers corrupting PIC registers, and I finally concluded a hardware solution would be best. This is not to say EMI requirements were not taken into account for the PIC hardware design at the outset - they were - but this approach further minimises potential conflicts.
Next I considered building dedicated monostable pulse generators based on CMOS 74-series 123 one-shots before I realised it was actually cheaper to buy complete instruments to do the job. Thus the front end timing is provided by three Lyons Instruments PG73N dual pulse generators [I30] which have a single shot push button as well as master oscillator, ext sync, and the added advantage of variable outputs up to ±10V.
All non-critical timing (e.g. NLO motor speed) is still provided by the µCs, which can also measure the pulse generator signals and display them on the GUI.
My first use for a PG73N was to feed its Ext input with a super low 0.3Hz signal from a Wavetek 154
pulse generator [I40], making channel A trigger the MK367 prototype's MOSFET with an +8V pulse and making channel B provide an inverted +3V pulse to trigger the Stellarnet spectrometer to verify the laser had fired.
PIC µCs
The LHC optical bench is 4 feet x 2 feet. A commercially viable design would ordinarily employ a single large processor with noise reduction techniques to interface all I/O across the bench, resulting in a huge birds nest of wiring. Since the project was never intended for commercial use, the hardware design takes the unusual step of incorporating a distributed processor system using a differential style
RS485 [D9] bus running duplex to avoid the need for clash detection hardware or software. The Tx signal is always present and when not communicating it is set high to permit remote energy scavenging.
Below is a link to Microchip's webpage that lets you select components according to category:
Below is a link to Microchip's webpage that lets you select µCs based upon their feature set:
https://www.microchip.com/maps/Microcontroller.aspx
Initially the number of suitable µCs was much more limited, resulting in my choices below. I am now constrained to these choices as the old CCS PICC compiler version I use does not have header files for later devices, and I can't justify paying a yearly subscription to keep it up to date. http://www.ccsinfo.com/content.php?page=compilers
Potentially I could construct new PIC18FXXX headers from what I assume are 229 Microchip C Compiler PIC18F headers found here: [S5], but it would be very tedious (I recall I found PICC a bit buggy, but far easier to use than Microchip's C compiler). It would be nice to have more than one UART but comms is so slow vs clock speed that software UARTs are viable, and the µCs below are adequate for the task.
Device Pkg I/O ROM RAM EEP Tn TX SPI ADC CMP IOC CCP IN ICP Comment
16F690-I/P DIP20 18 4k 256 256 012 1 1 12 2 A6B4 1 RA3 Y 20MHz General use
18F4455-I/P DIP40 35 24k 2048 256 0123 1 1 13 2 E4 2 RE3 Y 48MHz Master/PDA
Key:
Tn = number of onboard timers, TX = number of basic serial comms interfaces,
SPI = Serial Peripheral Interface, ADC = number of Analogue to Digital Converter channels,
CMP = number of analogue comparators, IOC = chip pins offering open collector/drain drivers,
CCP = number of digital comparators, IN = separate interrupt input chip pin,
ICP = In-Circuit Programming feature, (alpha numeric char pair e.g. A6 = PIC chip port pin)
My initial choice of the 18F4455 was driven by its inclusion of full USB 2.0 hardware support but subsequent investigation revealed the USB interface to be too complex and resource hungry. Since the chips were already purchased they were kept and instead, a standard UART implemented with a simple customised packet structure.
PIC µC DATASHEETS
ENCLOSURES
To maximise resilience in the electrically noisy environment of flashlamp powered lasers, all PICs reside in metal enclosures and all cables between them are shielded: USB 2.0 cables are used for comms and coaxial cables for power.
EMERGENCY OVERRIDE
we actually need the opposite of this - a mechanism that is powered and indicates failure by loss of power:
THERE IS A SHARED OPTICAL HARDWARE MASTER INTERRUPT THAT CAN BE USED BY PSCs IN THE CASE OF AN EMERGENCY: THIS IS SHARED BETWEEN ALL PSCs AND FORCES THE ENTIRE SYSTEM INTO A FAIL SAFE STATE IN THE EVENT OF A CATASTROPHIC EVENT AT ANY PSC. IT CAN BE DISABLED. EACH PSC CAN LIGHT AN LED INTO A SHARED FO, WHICH IT ALSO MONITORS. THE LED IS BATTERY POWERED, EACH BATTERY ON THE PSC. IF ANY PSC DETECTS LIGHT, IT ENTERS FAIL SAFE MODE. THE LED IS INDEPENDENT OF THE GUI AND VISIBLE TO THE USER. ONLY POWER SHUT DOWN CAN REMOVE IT, BUT THE FRONT PANEL SWITCHES (NOT THE FP CONTROLLER) CAN OVERRIDE THE PSCs.
PIC COMMS CABLING
A standard shielded 4-way USB 2.0 lead is physically arranged as a daisy-chain across all PICs but is actually just a feed-through so the next PIC lead can easily be connected.
USB lead pinout is as follows:
Pin USB LHC LHC use
1 - +5.5V Rx+ comms Tx+ from Master into all Slave PICs Rx+
2 - D- Tx- comms addressed Slave Tx- output to Master Rx-
3 - D+ Tx+ comms addressed Slave Tx+ output to Master Rx+
4 - 0V Rx- comms Tx- from Master into all Slave PICs Rx-
PIC POWER CABLING
Two power supply voltages are used on all PIC boards: +5V (logic) and +24V (peripherals).
+24V is routed around the system using coax: +24V inner core and 0V as the shield and return. Triax was the first choice but was considered too expensive. Each PIC runs off +5V from a LP2950-50LPRE3 microwatt regulator (+30Vin max) which drops the +24V to supply each PIC. The +24V supply is primarily used to control motors and heaters. Filtering prevents noise from entering the PIC and any sensitive circuitry.
In addition, power to all PICs is harvested from the incoming USB 2.0 Tx signal steady state high level voltage. The PIC monitors the +24V supply at all times and if it is removed the PIC runs off harvested energy, sets its '+24V power is off' status bit, responds to the next status prompt from the GUI (10Hz) and then enters sleep mode until +24V is re-applied. This removes any hazard from accidental removal of the power cable.
The combination of this and differential signaling minimises disruption from high energy switching. This modular approach simplifies system-wide wiring and localises all interfaces keeping wires short. Ideally a star-point system should be employed for power and grounds but for the low power PIC interfaces and to maintain the simplicity of the system, power is routed as feed-throughs in the same manner as the USB comms cables. High power laser switching circuitry and wiring is kept isolated and star-pointed where necessary.
PIC OSCILLATOR
All PICs run from an external 18.432MHz, 50ppm CMOS oscillator, which gives zero errors for UART baud rates up to 115200. The 18F4455 PICs have an internal PLL oscillator which derives an internal clock of 43.24MHz from the 18.432MHz oscillator.
PIC CODEVERSIONS
All PICs contain the same code build with optional compilation switches.
PIC COMMS
All communication originates from the PC-based GUI written in VC++, via the PC serial port using a standard USB 2.0 cable. The address 0 PSC (PIC slave Controller) which is an 18F4455, converts this to full duplex RS485 and relays it to all other PSCs. These are mostly 16F690 but where more resources are needed, 18F4455 too.
Each PIC responds only to a particular address in the serial communications protocol from the GUI and can only transmit on the shared Tx bus after receiving and acknowledging its dedicated command. Clashes are neither supported nor allowed.
PICs are addressed according to function as shown in the table below.
ADDRESSES
ADDR Type PIC NP Function PIC CLOCK
0 PSC 18F4455 10 USB 0 Trig 1 PCM 2 PDA 3 TC08 18.432MHz->PLL ~43MHz
1 PSC 16F690 01 MK580 Controller 18.432MHz
2 PSC 16F690 02 Ruby Controller 18.432MHz
3 PSC 18F4455 20 Front Panel Controller 18.432MHz->PLL ~43MHz
4 PSC 16F690 03 2HG motor & FB pot & Heater & Temp 18.432MHz
5 PSC 16F690 04 2HG pol motor & FB encoder 18.432MHz
6 PSC 16F690 05 4HG motor & FB pot & Heater & Temp 18.432MHz
7 PSC 16F690 06 4HG pol motor & FB encoder 18.432MHz
8 PSC 16F690 07 4 Fans & Flows witch & Level 18.432MHz
9 PSC 16F4455 30 Target Focus Rot Mot Detect Press 18.432MHz->PLL ~43MHz
A PSC 16F690 08 PCM401 shutter controller 18.432MHz (OPTIONAL)
B PSC 16F690 09 Bremsstrahlung Radiation Detect 18.432MHz (OPTIONAL)
C PSC 18F4455 40 GPIB Controller 18.432MHz->PLL ~43MHz (OPTIONAL)
D PSC Spare
E PSC Spare
F ALL - 00 General Broadcast
'NP' is not a field, but instead a count of how many of each type of PIC is used:
4 x 18F4455
9 x 16F690
PROTOCOL
The PIC address is part of the command protocol packet definition below:
|BB HH ADDR|RE CMD | CsumH | CsumL | Byte 1 |- - - - | Byte n |
|76 54 3210|76 543210|76543210|76543210|76543210|- - - - |76543210|
|nn nn nnnn|nn nnnnnn|nnnnnnnn|nnnnnnnn|nnnnnnnn|- - - - |nnnnnnnn|
| | | | | | | |
| 1st byte |2nd |3rd |4th |5th |6th |nth |
Where:
1. BB = #bytes:
00 = 0 data bytes ( 2 bytes total)
01 = 2 data bytes ( 6 bytes total)
10 = 4 data bytes ( 8 bytes total)
11 = FUTURE ENHANCEMENT
2. HH = hardware selection bits
3. ADDR = 14 PSC base addresses (+2 reserved)
4. R = 1 = Read, 0 = write
5. E = Expansion bit (command) (normally 0)
6. CMD = Command (64)
7. Csum = Checksum of entire command, a 16-bit value stored in CsumH, CsumL
This structure is partly designed to aid debugging by ensuring both the PSC address and instruction command are readily discernible in first two bytes of the serial data stream.
The number of bytes BB is in the first byte to initialise the Rx byte counter.
A maximum of 14 PSCs is addressable, with optional sub-division of hardware function provided by the E bit which also doubles up as an extra ms address bit. The R bit determines if the command is read or write; a zero byte command is by default neither read or write.
Address 15 is General Broadcast to all PSCs
A maximum of 64 commands is immediately obvious, with optional expansion to 128 variants using the E command extension bit that is normally 0. Each of these can be a Read or Write command as defined by the R bit. Commands that do not act on data and do not read or write are identified by setting the BB #bytes bits to 00.
The software section repeats this table and explains the protocol further.
The GUI is the bus master and initiates all commands.
Each PSC responds to GUI commands.
PIC HARDWARE IMPLEMENTATION
The system block diagram, black marker on a white board as it evolves, is below:
The boxes to the left represent PIC boards, with their address shown in the bottom right corner.
Triangles are electrical interface buffer circuits.
ADDR Function
0 USB 0 Trig 1 PCM 2 PDA 3 TC08:
USB I/F, LIBS init, PDA & Thermocouple samplers
1 MK580 Controller:
Essential timing signals and interlocks
2 Ruby Controller:
Essential timing signals and interlocks
3 Front Panel Controller:
Switches and LEDs to control the system
(but the GUI may supersede this)
4 2HG rotation motor controller:
Feedback pot, heater and temperature sensor
5 2HG polarisation motor:
Half waveplate motor and feedback encoder
6 4HG motor & FB pot & heater & temperature:
Feedback pot, heater and temperature sensor
7 4HG polarisation motor:
Half waveplate motor and feedback encoder
8 4 Fans & Flow switch & Level:
For water cooling loop
9 Target Focus Rotation Motor, Position detection,
Target rotation motor, focus detection, pressure
A PCM401 shutter controller (optional):
To block Bremsstrahlung, & maybe Q-switch
B Bremsstrahlung Radiation Detector (optional):
Experimental, may not be needed
C GPIB Controller (optional):
For the 7912AD if I can get it working
Ideally I would have used CAD to lay out my own PCBs and make them myself, but although I have used many CAD packages, considerable time has passed since then, and picking it up again is time consuming
and without that knowledge to hand, a pre-made PCB has the advantages of a silkscreen, through hole vias and tin plating. I therefore bulk-bought RKPK20 and RKPK40 PIC µC prototyping PCBs. I bought them from http://www.robotshop.com/uk - in 2020 they no longer sell them, but I still recommend them for useful stuff; Rapid Electronics does: https://www.rapidonline.com/Catalogue/Search?Query=rkpk
A word of warning to anyone contemplating in-circuit programming PICs on them with a Microchip PICkit - the programming header pinout is not the same! The PCB layout is also somewhat unprofessional (there are some bugs on the schematic and grounding is poor), but adequate.
I selected these PCBs because they are cheaper than the Microchip equivalents and have a 0.1" spacing development area that is ideal for interface electronics (SMD components can be added on modules, but soldering SMD chips is not my idea of fun). To begin with I built two 18F4455 prototype boards to get the serial protocol up and running and prove the GUI / hardware interface for the pressure sensor, and a DDS frequency synthesiser for another project.
ADD PHOTOS OF PCBs HERE
Below, initial design of rack-mounted front panel controller for MK367 and MK580:
Working away from my home and lab, I used the excellent free VA32 Virtual Scope as a low speed oscilloscope utilising the PC sound card as its input:
ADD SCREENSHOTS OF VIRTUAL SCOPE VA32 HERE
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